Due to the continual use of more and more electronics in vehicles, the Society of Automotive Engineers (SAE) encouraged the entire automotive industry to develop a standard data link, preferably a medium-speed (Class B) multiple access serial communications link. Already, SAE has established Recommended Practice J1850 (a set of technical requirements and parameters) and the industry has accepted a Class B data link as a J1850 as the recommended practice.
J1850 specifies use of symbols for communicating serial data over a communications bus. In variable pulse width modulation (VPWM) encoding, as used in the present invention, a symbol comprises a voltage logic level that extends for a period of time and then a voltage transition or edge.
The amount of time and the voltage level between trip points of the previous edge and the current edge defines the meaning of the symbol. For example, a logic zero bit which can be either a short low of 64 .mu.s or a long high of 128 .mu.s represents the time between edges or transitions of the VPWM signal. J1850 specifies 3.875 volts as a nominal receiver trip point voltage parameter.
To minimize EMC problems during each transition of waveforms containing symbol information, waveshaping of the VPWM edges must take place. To satisfy RFI requirements of signals that reach the bus, each edge must have a certain slope and corner shape.
Within a transceiver, problems result in trying to maintain consistent transmitted trip points. Since the trip point of the previous edge provides the point of reference for the current edge, a problem occurs if the trip points of the transitions occur at different times.
J1850 specifies that communication busses may be a single wires routed throughout the network.
In prior systems, reshaping VPWM pulses to satisfy RFI requirements occur, but usually without considering maintaining consistent transmitted pulse trip-points. Probably the prior system designers focus more attention to problems of voltage offset between nodes rather than transmitting clean pulses.
In prior systems, to address noise spikes on the bus, designers have incorporated filtering schemes. Usually, filters used with line drivers help in eliminating short duration noise spikes and transition noise from incoming waveforms. But, such arrangements cause delays in transition time of the pulses.
In prior single wire bus systems, symbol pulse widths have not been affected by multiple nodes trying to transmit at the same time during arbitration. This is because a single node effectively dominates each transition. It is the first node to leave the passive state or the last node to leave the active state. However, feed-back type approaches have been employed to maintain the integrity of voltage levels and the shape of pulses reshaped to combat EMI noise. Such systems tend to be prone to some oscillation and weakness with respect to dealing with pulse width distortion due to undesirable pulses on the single-wire bus.
In an effort to find a bus driver capable of transmitting symbol messages over a single wire bus with minimal distortion of symbol time spans, and with some immunity from undesirable noise spikes, a search took place to find bus driver arrangements which could control current and voltage changes, including spikes without destroying the integrity of the transmitted messages. This search resulted in the present invention which uses voltage levels of the inputed pulse signals to control current signals on the bus in a manner which maintains the integrity of the transmitted messages.